\doxysection{RCC\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_r_c_c___type_def}{}\label{struct_r_c_c___type_def}\index{RCC\_TypeDef@{RCC\_TypeDef}}


Reset and Clock Control.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_abcb9ff48b9afb990283fefad0554b5b3}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a17b0cadfbcca7ed3b6aa4ef43c6c12f9}{HSICFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a1694a01e1a23db1694288fb3a86e9f18}{CRRCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_aa2d7bfc4c20fea2c980bda5114e31384}{CSICFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a0721b1b729c313211126709559fad371}{CFGR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_aa121f96a873fb9ff4f651c9e636efec3}{RESERVED1}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a2e31ab15dc0dfba2aee81b30b792e4c5}{D1\+CFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a948edd9da43a665b25c71a00ea760ca2}{D2\+CFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a9ed9e59d8a7f3f567b41d5f57f6f5acd}{D3\+CFGR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a94cb7e7b923ebacab99c967d0f808235}{RESERVED2}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a627836f05c0e3a9545605318e6447adf}{PLLCKSELR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a2a7ccb4e23cb05a574f243f6278b7b26}{PLLCFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a57bcbce85db68d77ed5cbf18a10f9d3f}{PLL1\+DIVR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a2134cb67af4b948e7d6d6c656e8837d2}{PLL1\+FRACR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ab258f4bfa80f5c8f6cc5440df30c0909}{PLL2\+DIVR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ad8bccd45fde1d630c5bb4f035e6ea0fb}{PLL2\+FRACR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a59d4bd0595fcfd4ca87cc2dd17e7eb2a}{PLL3\+DIVR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_afd88563b698968b152eed83be41f0334}{PLL3\+FRACR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a13aa031d83f9d927683781577eb153a2}{RESERVED3}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a7edcbbd70a162b0896b1ee0f465b13b0}{D1\+CCIPR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ae690e1e6b03fba505a7937345ca30021}{D2\+CCIP1R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a9168a7090cfa4125c517c5aaaa3baae1}{D2\+CCIP2R}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a0456a2f98ab35da5c66d2c25ed6b5848}{D3\+CCIPR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a0f009e4bd1777ac1b86ca27e23361a0e}{RESERVED4}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a6d0c293e1198ffec4802a19328ba73bb}{CIER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_afee6ba7ba2583577492d14f08a1a5e74}{CIFR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a28e7b1071afa5b6c98f8050890159b05}{CICR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_aa564eba028e76a5ed58ac578d1842bd2}{RESERVED5}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a05be375db50e8c9dd24fb3bcf42d7cf1}{BDCR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a7e913b8bf59d4351e1f3d19387bd05b9}{CSR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_acc8c36a4234b8fbc9d68f52a2e22e69e}{RESERVED6}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a39a90d838fbd0b8515f03e4a1be6374f}{AHB3\+RSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ad6abf71a348744aa3f2b7e8b214c1ca4}{AHB1\+RSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a343e0230ded55920ff2a04fbde0e5bcd}{AHB2\+RSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ad1d8a19aa9532b446147a431f3b19481}{AHB4\+RSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_acf2c6fb3d252dbb6c733507e5f7ed7b3}{APB3\+RSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a92d5bc4f6d23c566d55f7dd477fadbe5}{APB1\+LRSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a37fa3ab0516ab6fc0ecb604850353075}{APB1\+HRSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a4491ab20a44b70bf7abd247791676a59}{APB2\+RSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_aabdd13237767f4de5900e52285337543}{APB4\+RSTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a5c3f5140ae596eaa834f4f3a85765f95}{GCR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_af64a7560ef9f8315e17c5a622773a7f8}{RESERVED8}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ada0be86dd42582ae99b43868fc13c08c}{D3\+AMR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a6c05a2164a27ecb7153025d919e9aaf7}{RESERVED11}} \mbox{[}9\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_af24273f1ea29293cf757fc13c5c030ea}{RSR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ad4ea7be562b42e2ae1a84db44121195d}{AHB3\+ENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_af58a7ad868f07f8759eac3e31b6fa79e}{AHB1\+ENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_af326cb98c318fc08894a8dd79c2c675f}{AHB2\+ENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a9378e612125c10c30957cc6881c7ad31}{AHB4\+ENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a1910f7dcab13f4550fb5634fad3e5aea}{APB3\+ENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a9670ffa5d9a81aab33733ac14a2526fd}{APB1\+LENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a60744135b166d9236404b1b252935fe6}{APB1\+HENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a619b4c22f630a269dfd0c331f90f6868}{APB2\+ENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_afc545cbc90c38345d14c33c179f0396e}{APB4\+ENR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a5b7fd24a7a998b373159c15708ca0b17}{RESERVED12}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a95edda857c3725bfb410d3a4707edfd8}{AHB3\+LPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a89d6c21f02196b7f59bcc30c1061dd87}{AHB1\+LPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a1de344446cba3f4dd15c56fbe20eb0dd}{AHB2\+LPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a18452fdca17282224b17a61cf45b19e6}{AHB4\+LPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_affe1ec42c27813e04812871241bc7eb0}{APB3\+LPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_aac50d43321b6672ebaa45a61059b7e48}{APB1\+LLPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_ab4bb1b1ecf6207089ec5b11545d17b0a}{APB1\+HLPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a7e46c65220f00a6858a5b35b74a37b51}{APB2\+LPENR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_af2ea825e048b274a599cea838ab46c4a}{APB4\+LPENR}}
\item 
uint32\+\_\+t \mbox{\hyperlink{struct_r_c_c___type_def_a139d79f321cdaea79884fd2c45c7fc1a}{RESERVED13}} \mbox{[}4\mbox{]}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Reset and Clock Control. 

\label{doc-variable-members}
\Hypertarget{struct_r_c_c___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_r_c_c___type_def_af58a7ad868f07f8759eac3e31b6fa79e}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB1ENR@{AHB1ENR}}
\index{AHB1ENR@{AHB1ENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB1ENR}{AHB1ENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_af58a7ad868f07f8759eac3e31b6fa79e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB1\+ENR}

RCC AHB1 peripheral clock register, Address offset\+: 0x\+D8 \Hypertarget{struct_r_c_c___type_def_a89d6c21f02196b7f59bcc30c1061dd87}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB1LPENR@{AHB1LPENR}}
\index{AHB1LPENR@{AHB1LPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB1LPENR}{AHB1LPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a89d6c21f02196b7f59bcc30c1061dd87} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB1\+LPENR}

RCC AHB1 peripheral sleep clock register, Address offset\+: 0x100 \Hypertarget{struct_r_c_c___type_def_ad6abf71a348744aa3f2b7e8b214c1ca4}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB1RSTR@{AHB1RSTR}}
\index{AHB1RSTR@{AHB1RSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB1RSTR}{AHB1RSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ad6abf71a348744aa3f2b7e8b214c1ca4} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB1\+RSTR}

RCC AHB1 peripheral reset register, Address offset\+: 0x80 \Hypertarget{struct_r_c_c___type_def_af326cb98c318fc08894a8dd79c2c675f}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB2ENR@{AHB2ENR}}
\index{AHB2ENR@{AHB2ENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB2ENR}{AHB2ENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_af326cb98c318fc08894a8dd79c2c675f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB2\+ENR}

RCC AHB2 peripheral clock register, Address offset\+: 0x\+DC \Hypertarget{struct_r_c_c___type_def_a1de344446cba3f4dd15c56fbe20eb0dd}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB2LPENR@{AHB2LPENR}}
\index{AHB2LPENR@{AHB2LPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB2LPENR}{AHB2LPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a1de344446cba3f4dd15c56fbe20eb0dd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB2\+LPENR}

RCC AHB2 peripheral sleep clock register, Address offset\+: 0x104 \Hypertarget{struct_r_c_c___type_def_a343e0230ded55920ff2a04fbde0e5bcd}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB2RSTR@{AHB2RSTR}}
\index{AHB2RSTR@{AHB2RSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB2RSTR}{AHB2RSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a343e0230ded55920ff2a04fbde0e5bcd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB2\+RSTR}

RCC AHB2 peripheral reset register, Address offset\+: 0x84 \Hypertarget{struct_r_c_c___type_def_ad4ea7be562b42e2ae1a84db44121195d}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB3ENR@{AHB3ENR}}
\index{AHB3ENR@{AHB3ENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB3ENR}{AHB3ENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ad4ea7be562b42e2ae1a84db44121195d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB3\+ENR}

RCC AHB3 peripheral clock register, Address offset\+: 0x\+D4 \Hypertarget{struct_r_c_c___type_def_a95edda857c3725bfb410d3a4707edfd8}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB3LPENR@{AHB3LPENR}}
\index{AHB3LPENR@{AHB3LPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB3LPENR}{AHB3LPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a95edda857c3725bfb410d3a4707edfd8} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB3\+LPENR}

RCC AHB3 peripheral sleep clock register, Address offset\+: 0x\+FC \Hypertarget{struct_r_c_c___type_def_a39a90d838fbd0b8515f03e4a1be6374f}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB3RSTR@{AHB3RSTR}}
\index{AHB3RSTR@{AHB3RSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB3RSTR}{AHB3RSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a39a90d838fbd0b8515f03e4a1be6374f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB3\+RSTR}

RCC AHB3 peripheral reset register, Address offset\+: 0x7C \Hypertarget{struct_r_c_c___type_def_a9378e612125c10c30957cc6881c7ad31}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB4ENR@{AHB4ENR}}
\index{AHB4ENR@{AHB4ENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB4ENR}{AHB4ENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a9378e612125c10c30957cc6881c7ad31} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB4\+ENR}

RCC AHB4 peripheral clock register, Address offset\+: 0x\+E0 \Hypertarget{struct_r_c_c___type_def_a18452fdca17282224b17a61cf45b19e6}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB4LPENR@{AHB4LPENR}}
\index{AHB4LPENR@{AHB4LPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB4LPENR}{AHB4LPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a18452fdca17282224b17a61cf45b19e6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB4\+LPENR}

RCC AHB4 peripheral sleep clock register, Address offset\+: 0x108 \Hypertarget{struct_r_c_c___type_def_ad1d8a19aa9532b446147a431f3b19481}\index{RCC\_TypeDef@{RCC\_TypeDef}!AHB4RSTR@{AHB4RSTR}}
\index{AHB4RSTR@{AHB4RSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{AHB4RSTR}{AHB4RSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ad1d8a19aa9532b446147a431f3b19481} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+AHB4\+RSTR}

RCC AHB4 peripheral reset register, Address offset\+: 0x88 \Hypertarget{struct_r_c_c___type_def_a60744135b166d9236404b1b252935fe6}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB1HENR@{APB1HENR}}
\index{APB1HENR@{APB1HENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1HENR}{APB1HENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a60744135b166d9236404b1b252935fe6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB1\+HENR}

RCC APB1 peripheral clock High Word register, Address offset\+: 0x\+EC \Hypertarget{struct_r_c_c___type_def_ab4bb1b1ecf6207089ec5b11545d17b0a}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB1HLPENR@{APB1HLPENR}}
\index{APB1HLPENR@{APB1HLPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1HLPENR}{APB1HLPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ab4bb1b1ecf6207089ec5b11545d17b0a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB1\+HLPENR}

RCC APB1 peripheral sleep clock High Word register, Address offset\+: 0x114 \Hypertarget{struct_r_c_c___type_def_a37fa3ab0516ab6fc0ecb604850353075}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB1HRSTR@{APB1HRSTR}}
\index{APB1HRSTR@{APB1HRSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1HRSTR}{APB1HRSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a37fa3ab0516ab6fc0ecb604850353075} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB1\+HRSTR}

RCC APB1 peripheral reset High Word register, Address offset\+: 0x94 \Hypertarget{struct_r_c_c___type_def_a9670ffa5d9a81aab33733ac14a2526fd}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB1LENR@{APB1LENR}}
\index{APB1LENR@{APB1LENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1LENR}{APB1LENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a9670ffa5d9a81aab33733ac14a2526fd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB1\+LENR}

RCC APB1 peripheral clock Low Word register, Address offset\+: 0x\+E8 \Hypertarget{struct_r_c_c___type_def_aac50d43321b6672ebaa45a61059b7e48}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB1LLPENR@{APB1LLPENR}}
\index{APB1LLPENR@{APB1LLPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1LLPENR}{APB1LLPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_aac50d43321b6672ebaa45a61059b7e48} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB1\+LLPENR}

RCC APB1 peripheral sleep clock Low Word register, Address offset\+: 0x110 \Hypertarget{struct_r_c_c___type_def_a92d5bc4f6d23c566d55f7dd477fadbe5}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB1LRSTR@{APB1LRSTR}}
\index{APB1LRSTR@{APB1LRSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB1LRSTR}{APB1LRSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a92d5bc4f6d23c566d55f7dd477fadbe5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB1\+LRSTR}

RCC APB1 peripheral reset Low Word register, Address offset\+: 0x90 \Hypertarget{struct_r_c_c___type_def_a619b4c22f630a269dfd0c331f90f6868}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB2ENR@{APB2ENR}}
\index{APB2ENR@{APB2ENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB2ENR}{APB2ENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a619b4c22f630a269dfd0c331f90f6868} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB2\+ENR}

RCC APB2 peripheral clock register, Address offset\+: 0x\+F0 \Hypertarget{struct_r_c_c___type_def_a7e46c65220f00a6858a5b35b74a37b51}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB2LPENR@{APB2LPENR}}
\index{APB2LPENR@{APB2LPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB2LPENR}{APB2LPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a7e46c65220f00a6858a5b35b74a37b51} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB2\+LPENR}

RCC APB2 peripheral sleep clock register, Address offset\+: 0x118 \Hypertarget{struct_r_c_c___type_def_a4491ab20a44b70bf7abd247791676a59}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB2RSTR@{APB2RSTR}}
\index{APB2RSTR@{APB2RSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB2RSTR}{APB2RSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a4491ab20a44b70bf7abd247791676a59} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB2\+RSTR}

RCC APB2 peripheral reset register, Address offset\+: 0x98 \Hypertarget{struct_r_c_c___type_def_a1910f7dcab13f4550fb5634fad3e5aea}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB3ENR@{APB3ENR}}
\index{APB3ENR@{APB3ENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB3ENR}{APB3ENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a1910f7dcab13f4550fb5634fad3e5aea} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB3\+ENR}

RCC APB3 peripheral clock register, Address offset\+: 0x\+E4 \Hypertarget{struct_r_c_c___type_def_affe1ec42c27813e04812871241bc7eb0}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB3LPENR@{APB3LPENR}}
\index{APB3LPENR@{APB3LPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB3LPENR}{APB3LPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_affe1ec42c27813e04812871241bc7eb0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB3\+LPENR}

RCC APB3 peripheral sleep clock register, Address offset\+: 0x10C \Hypertarget{struct_r_c_c___type_def_acf2c6fb3d252dbb6c733507e5f7ed7b3}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB3RSTR@{APB3RSTR}}
\index{APB3RSTR@{APB3RSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB3RSTR}{APB3RSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_acf2c6fb3d252dbb6c733507e5f7ed7b3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB3\+RSTR}

RCC APB3 peripheral reset register, Address offset\+: 0x8C \Hypertarget{struct_r_c_c___type_def_afc545cbc90c38345d14c33c179f0396e}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB4ENR@{APB4ENR}}
\index{APB4ENR@{APB4ENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB4ENR}{APB4ENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_afc545cbc90c38345d14c33c179f0396e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB4\+ENR}

RCC APB4 peripheral clock register, Address offset\+: 0x\+F4 \Hypertarget{struct_r_c_c___type_def_af2ea825e048b274a599cea838ab46c4a}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB4LPENR@{APB4LPENR}}
\index{APB4LPENR@{APB4LPENR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB4LPENR}{APB4LPENR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_af2ea825e048b274a599cea838ab46c4a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB4\+LPENR}

RCC APB4 peripheral sleep clock register, Address offset\+: 0x11C \Hypertarget{struct_r_c_c___type_def_aabdd13237767f4de5900e52285337543}\index{RCC\_TypeDef@{RCC\_TypeDef}!APB4RSTR@{APB4RSTR}}
\index{APB4RSTR@{APB4RSTR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{APB4RSTR}{APB4RSTR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_aabdd13237767f4de5900e52285337543} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+APB4\+RSTR}

RCC APB4 peripheral reset register, Address offset\+: 0x9C \Hypertarget{struct_r_c_c___type_def_a05be375db50e8c9dd24fb3bcf42d7cf1}\index{RCC\_TypeDef@{RCC\_TypeDef}!BDCR@{BDCR}}
\index{BDCR@{BDCR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{BDCR}{BDCR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a05be375db50e8c9dd24fb3bcf42d7cf1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+BDCR}

RCC Vswitch Backup Domain Control Register, Address offset\+: 0x70 \Hypertarget{struct_r_c_c___type_def_a0721b1b729c313211126709559fad371}\index{RCC\_TypeDef@{RCC\_TypeDef}!CFGR@{CFGR}}
\index{CFGR@{CFGR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR}{CFGR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a0721b1b729c313211126709559fad371} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CFGR}

RCC clock configuration register, Address offset\+: 0x10 \Hypertarget{struct_r_c_c___type_def_a28e7b1071afa5b6c98f8050890159b05}\index{RCC\_TypeDef@{RCC\_TypeDef}!CICR@{CICR}}
\index{CICR@{CICR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CICR}{CICR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a28e7b1071afa5b6c98f8050890159b05} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CICR}

RCC Clock Source Interrupt Clear Register Address offset\+: 0x68 \Hypertarget{struct_r_c_c___type_def_a6d0c293e1198ffec4802a19328ba73bb}\index{RCC\_TypeDef@{RCC\_TypeDef}!CIER@{CIER}}
\index{CIER@{CIER}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CIER}{CIER}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a6d0c293e1198ffec4802a19328ba73bb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CIER}

RCC Clock Source Interrupt Enable Register Address offset\+: 0x60 \Hypertarget{struct_r_c_c___type_def_afee6ba7ba2583577492d14f08a1a5e74}\index{RCC\_TypeDef@{RCC\_TypeDef}!CIFR@{CIFR}}
\index{CIFR@{CIFR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CIFR}{CIFR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_afee6ba7ba2583577492d14f08a1a5e74} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CIFR}

RCC Clock Source Interrupt Flag Register Address offset\+: 0x64 \Hypertarget{struct_r_c_c___type_def_abcb9ff48b9afb990283fefad0554b5b3}\index{RCC\_TypeDef@{RCC\_TypeDef}!CR@{CR}}
\index{CR@{CR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_abcb9ff48b9afb990283fefad0554b5b3} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CR}

RCC clock control register, Address offset\+: 0x00 \Hypertarget{struct_r_c_c___type_def_a1694a01e1a23db1694288fb3a86e9f18}\index{RCC\_TypeDef@{RCC\_TypeDef}!CRRCR@{CRRCR}}
\index{CRRCR@{CRRCR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CRRCR}{CRRCR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a1694a01e1a23db1694288fb3a86e9f18} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CRRCR}

Clock Recovery RC Register, Address offset\+: 0x08 \Hypertarget{struct_r_c_c___type_def_aa2d7bfc4c20fea2c980bda5114e31384}\index{RCC\_TypeDef@{RCC\_TypeDef}!CSICFGR@{CSICFGR}}
\index{CSICFGR@{CSICFGR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSICFGR}{CSICFGR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_aa2d7bfc4c20fea2c980bda5114e31384} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CSICFGR}

CSI Clock Calibration Register, Address offset\+: 0x0C \Hypertarget{struct_r_c_c___type_def_a7e913b8bf59d4351e1f3d19387bd05b9}\index{RCC\_TypeDef@{RCC\_TypeDef}!CSR@{CSR}}
\index{CSR@{CSR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CSR}{CSR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a7e913b8bf59d4351e1f3d19387bd05b9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+CSR}

RCC clock control \& status register, Address offset\+: 0x74 \Hypertarget{struct_r_c_c___type_def_a7edcbbd70a162b0896b1ee0f465b13b0}\index{RCC\_TypeDef@{RCC\_TypeDef}!D1CCIPR@{D1CCIPR}}
\index{D1CCIPR@{D1CCIPR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D1CCIPR}{D1CCIPR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a7edcbbd70a162b0896b1ee0f465b13b0} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D1\+CCIPR}

RCC Domain 1 Kernel Clock Configuration Register Address offset\+: 0x4C \Hypertarget{struct_r_c_c___type_def_a2e31ab15dc0dfba2aee81b30b792e4c5}\index{RCC\_TypeDef@{RCC\_TypeDef}!D1CFGR@{D1CFGR}}
\index{D1CFGR@{D1CFGR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D1CFGR}{D1CFGR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a2e31ab15dc0dfba2aee81b30b792e4c5} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D1\+CFGR}

RCC Domain 1 configuration register, Address offset\+: 0x18 \Hypertarget{struct_r_c_c___type_def_ae690e1e6b03fba505a7937345ca30021}\index{RCC\_TypeDef@{RCC\_TypeDef}!D2CCIP1R@{D2CCIP1R}}
\index{D2CCIP1R@{D2CCIP1R}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D2CCIP1R}{D2CCIP1R}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ae690e1e6b03fba505a7937345ca30021} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D2\+CCIP1R}

RCC Domain 2 Kernel Clock Configuration Register Address offset\+: 0x50 \Hypertarget{struct_r_c_c___type_def_a9168a7090cfa4125c517c5aaaa3baae1}\index{RCC\_TypeDef@{RCC\_TypeDef}!D2CCIP2R@{D2CCIP2R}}
\index{D2CCIP2R@{D2CCIP2R}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D2CCIP2R}{D2CCIP2R}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a9168a7090cfa4125c517c5aaaa3baae1} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D2\+CCIP2R}

RCC Domain 2 Kernel Clock Configuration Register Address offset\+: 0x54 \Hypertarget{struct_r_c_c___type_def_a948edd9da43a665b25c71a00ea760ca2}\index{RCC\_TypeDef@{RCC\_TypeDef}!D2CFGR@{D2CFGR}}
\index{D2CFGR@{D2CFGR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D2CFGR}{D2CFGR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a948edd9da43a665b25c71a00ea760ca2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D2\+CFGR}

RCC Domain 2 configuration register, Address offset\+: 0x1C \Hypertarget{struct_r_c_c___type_def_ada0be86dd42582ae99b43868fc13c08c}\index{RCC\_TypeDef@{RCC\_TypeDef}!D3AMR@{D3AMR}}
\index{D3AMR@{D3AMR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3AMR}{D3AMR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ada0be86dd42582ae99b43868fc13c08c} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D3\+AMR}

RCC Domain 3 Autonomous Mode Register, Address offset\+: 0x\+A8 \Hypertarget{struct_r_c_c___type_def_a0456a2f98ab35da5c66d2c25ed6b5848}\index{RCC\_TypeDef@{RCC\_TypeDef}!D3CCIPR@{D3CCIPR}}
\index{D3CCIPR@{D3CCIPR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3CCIPR}{D3CCIPR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a0456a2f98ab35da5c66d2c25ed6b5848} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D3\+CCIPR}

RCC Domain 3 Kernel Clock Configuration Register Address offset\+: 0x58 \Hypertarget{struct_r_c_c___type_def_a9ed9e59d8a7f3f567b41d5f57f6f5acd}\index{RCC\_TypeDef@{RCC\_TypeDef}!D3CFGR@{D3CFGR}}
\index{D3CFGR@{D3CFGR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{D3CFGR}{D3CFGR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a9ed9e59d8a7f3f567b41d5f57f6f5acd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+D3\+CFGR}

RCC Domain 3 configuration register, Address offset\+: 0x20 \Hypertarget{struct_r_c_c___type_def_a5c3f5140ae596eaa834f4f3a85765f95}\index{RCC\_TypeDef@{RCC\_TypeDef}!GCR@{GCR}}
\index{GCR@{GCR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{GCR}{GCR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a5c3f5140ae596eaa834f4f3a85765f95} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+GCR}

RCC RCC Global Control Register, Address offset\+: 0x\+A0 \Hypertarget{struct_r_c_c___type_def_a17b0cadfbcca7ed3b6aa4ef43c6c12f9}\index{RCC\_TypeDef@{RCC\_TypeDef}!HSICFGR@{HSICFGR}}
\index{HSICFGR@{HSICFGR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HSICFGR}{HSICFGR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a17b0cadfbcca7ed3b6aa4ef43c6c12f9} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+HSICFGR}

HSI Clock Calibration Register, Address offset\+: 0x04 \Hypertarget{struct_r_c_c___type_def_a57bcbce85db68d77ed5cbf18a10f9d3f}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLL1DIVR@{PLL1DIVR}}
\index{PLL1DIVR@{PLL1DIVR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLL1DIVR}{PLL1DIVR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a57bcbce85db68d77ed5cbf18a10f9d3f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLL1\+DIVR}

RCC PLL1 Dividers Configuration Register, Address offset\+: 0x30 \Hypertarget{struct_r_c_c___type_def_a2134cb67af4b948e7d6d6c656e8837d2}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLL1FRACR@{PLL1FRACR}}
\index{PLL1FRACR@{PLL1FRACR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLL1FRACR}{PLL1FRACR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a2134cb67af4b948e7d6d6c656e8837d2} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLL1\+FRACR}

RCC PLL1 Fractional Divider Configuration Register, Address offset\+: 0x34 \Hypertarget{struct_r_c_c___type_def_ab258f4bfa80f5c8f6cc5440df30c0909}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLL2DIVR@{PLL2DIVR}}
\index{PLL2DIVR@{PLL2DIVR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2DIVR}{PLL2DIVR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ab258f4bfa80f5c8f6cc5440df30c0909} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLL2\+DIVR}

RCC PLL2 Dividers Configuration Register, Address offset\+: 0x38 \Hypertarget{struct_r_c_c___type_def_ad8bccd45fde1d630c5bb4f035e6ea0fb}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLL2FRACR@{PLL2FRACR}}
\index{PLL2FRACR@{PLL2FRACR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLL2FRACR}{PLL2FRACR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_ad8bccd45fde1d630c5bb4f035e6ea0fb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLL2\+FRACR}

RCC PLL2 Fractional Divider Configuration Register, Address offset\+: 0x3C \Hypertarget{struct_r_c_c___type_def_a59d4bd0595fcfd4ca87cc2dd17e7eb2a}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLL3DIVR@{PLL3DIVR}}
\index{PLL3DIVR@{PLL3DIVR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3DIVR}{PLL3DIVR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a59d4bd0595fcfd4ca87cc2dd17e7eb2a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLL3\+DIVR}

RCC PLL3 Dividers Configuration Register, Address offset\+: 0x40 \Hypertarget{struct_r_c_c___type_def_afd88563b698968b152eed83be41f0334}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLL3FRACR@{PLL3FRACR}}
\index{PLL3FRACR@{PLL3FRACR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLL3FRACR}{PLL3FRACR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_afd88563b698968b152eed83be41f0334} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLL3\+FRACR}

RCC PLL3 Fractional Divider Configuration Register, Address offset\+: 0x44 \Hypertarget{struct_r_c_c___type_def_a2a7ccb4e23cb05a574f243f6278b7b26}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLLCFGR@{PLLCFGR}}
\index{PLLCFGR@{PLLCFGR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLLCFGR}{PLLCFGR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a2a7ccb4e23cb05a574f243f6278b7b26} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLLCFGR}

RCC PLLs Configuration Register, Address offset\+: 0x2C \Hypertarget{struct_r_c_c___type_def_a627836f05c0e3a9545605318e6447adf}\index{RCC\_TypeDef@{RCC\_TypeDef}!PLLCKSELR@{PLLCKSELR}}
\index{PLLCKSELR@{PLLCKSELR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PLLCKSELR}{PLLCKSELR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a627836f05c0e3a9545605318e6447adf} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+PLLCKSELR}

RCC PLLs Clock Source Selection Register, Address offset\+: 0x28 \Hypertarget{struct_r_c_c___type_def_aa121f96a873fb9ff4f651c9e636efec3}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_aa121f96a873fb9ff4f651c9e636efec3} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED1}

Reserved, Address offset\+: 0x14 \Hypertarget{struct_r_c_c___type_def_a6c05a2164a27ecb7153025d919e9aaf7}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED11@{RESERVED11}}
\index{RESERVED11@{RESERVED11}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED11}{RESERVED11}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a6c05a2164a27ecb7153025d919e9aaf7} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED11\mbox{[}9\mbox{]}}

Reserved, 0x\+AC-\/0x\+CC Address offset\+: 0x\+AC \Hypertarget{struct_r_c_c___type_def_a5b7fd24a7a998b373159c15708ca0b17}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED12@{RESERVED12}}
\index{RESERVED12@{RESERVED12}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED12}{RESERVED12}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a5b7fd24a7a998b373159c15708ca0b17} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED12}

Reserved, Address offset\+: 0x\+F8 \Hypertarget{struct_r_c_c___type_def_a139d79f321cdaea79884fd2c45c7fc1a}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED13@{RESERVED13}}
\index{RESERVED13@{RESERVED13}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED13}{RESERVED13}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a139d79f321cdaea79884fd2c45c7fc1a} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED13\mbox{[}4\mbox{]}}

Reserved, 0x120-\/0x12C Address offset\+: 0x120 \Hypertarget{struct_r_c_c___type_def_a94cb7e7b923ebacab99c967d0f808235}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a94cb7e7b923ebacab99c967d0f808235} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED2}

Reserved, Address offset\+: 0x24 \Hypertarget{struct_r_c_c___type_def_a13aa031d83f9d927683781577eb153a2}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED3@{RESERVED3}}
\index{RESERVED3@{RESERVED3}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED3}{RESERVED3}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a13aa031d83f9d927683781577eb153a2} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED3}

Reserved, Address offset\+: 0x48 \Hypertarget{struct_r_c_c___type_def_a0f009e4bd1777ac1b86ca27e23361a0e}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED4@{RESERVED4}}
\index{RESERVED4@{RESERVED4}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED4}{RESERVED4}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_a0f009e4bd1777ac1b86ca27e23361a0e} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED4}

Reserved, Address offset\+: 0x5C \Hypertarget{struct_r_c_c___type_def_aa564eba028e76a5ed58ac578d1842bd2}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED5@{RESERVED5}}
\index{RESERVED5@{RESERVED5}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED5}{RESERVED5}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_aa564eba028e76a5ed58ac578d1842bd2} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED5}

Reserved, Address offset\+: 0x6C \Hypertarget{struct_r_c_c___type_def_acc8c36a4234b8fbc9d68f52a2e22e69e}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED6@{RESERVED6}}
\index{RESERVED6@{RESERVED6}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED6}{RESERVED6}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_acc8c36a4234b8fbc9d68f52a2e22e69e} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED6}

Reserved, Address offset\+: 0x78 \Hypertarget{struct_r_c_c___type_def_af64a7560ef9f8315e17c5a622773a7f8}\index{RCC\_TypeDef@{RCC\_TypeDef}!RESERVED8@{RESERVED8}}
\index{RESERVED8@{RESERVED8}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED8}{RESERVED8}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_af64a7560ef9f8315e17c5a622773a7f8} 
uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RESERVED8}

Reserved, Address offset\+: 0x\+A4 \Hypertarget{struct_r_c_c___type_def_af24273f1ea29293cf757fc13c5c030ea}\index{RCC\_TypeDef@{RCC\_TypeDef}!RSR@{RSR}}
\index{RSR@{RSR}!RCC\_TypeDef@{RCC\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RSR}{RSR}}
{\footnotesize\ttfamily \label{struct_r_c_c___type_def_af24273f1ea29293cf757fc13c5c030ea} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t RCC\+\_\+\+Type\+Def\+::\+RSR}

RCC Reset status register, Address offset\+: 0x\+D0 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
